SystemVerilog:$finishの引数
IEEE規格では以下のように定義されています。
- Table 20.1 Diagnostics for $finish
Argument value | Diagnostic message |
---|---|
0 | Prints nothing |
1 | Prints simulation time and location |
2 | Prints simulation time, location, and statistics about the memory and central processing unit (CPU) time used in simulation |
各出力を試してみました。
module testbench (); initial begin #100; $display("--- hoge ---"); $finish(n); // n = 0,1,2 end endmodule: testbench
- $finish(0)
# --- hoge ---
- $finish(1)
# --- hoge --- # ** Note: $finish : test.sv(8) # Time: 100 ns Iteration: 0 Instance: /testbench
- $finish(2)
# --- hoge --- # ** Note: Data structure takes 2981936 bytes of memory # Process time 0.00 seconds # $finish : test.sv(8) # Time: 100 ns Iteration: 0 Instance: /testbench